Category:1967 births
Category:Living people
Category:American women writers
Category:American women journalists
Category:People from Chico, California
Category:Businesspeople from California
Category:Writers from California
Category:Disney people
Category:American writers of Mexican descent1. Field of the Invention
The present invention generally relates to a system for detecting defects on a substrate, and more specifically, to a system for detecting defects on a substrate including circuits and logic blocks.
2. Description of the Related Art
FIG. 1 shows a conventional defect detection system. The conventional defect detection system of FIG. 1 comprises a defect detection unit 10 and a control unit 11. The defect detection unit 10 is used for detecting defects on a substrate 12, such as a wafer. The defect detection unit 10 comprises a defect scan pattern generator 13 and a scan circuit 14. The defect scan pattern generator 13 generates a defect scan pattern according to a control signal from the control unit 11. The scan circuit 14 comprises a plurality of scan blocks 15. Each of the scan blocks 15 is a functional circuit block such as a circuit block that is a unit of a system-on-chip (SoC) for functional blocks such as CPU, memory, analog circuit, or digital circuit.
The defect scan pattern generator 13 further comprises a scan point memory (SPM) for storing and recalling the defect scan pattern. The defect detection system of FIG. 1 further comprises a comparator 16 and a pattern comparator 17. The comparator 16 is connected to the scan circuit 14 and to the scan point memory (SPM) to compare the defect scan pattern generated by the defect scan pattern generator 13 to a predetermined value, and to output a defect signal as a result of the comparison. The pattern comparator 17 is connected to the comparator 16 to compare the defect signal output from the comparator 16 to a defect signal stored in the pattern comparator 17 to generate a defect signal output for the control unit 11. The control unit 11 is connected to the pattern comparator 17 to generate a control signal for the defect scan pattern generator 13 and the scan circuit 14 according to the defect signal output from the pattern comparator 17.
For example, the control unit 11 generates a control signal of “0” for the scan point memory (SPM), which is a defect scan pattern generating unit in the defect scan pattern generator 13, in response to a defect signal output from the pattern comparator 17, and generates a control signal of � be359ba680
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